ASIC analogique

  • See this page in english

    En bref

  • Nombre d'heures : 3.5 HC + 35 HBE
  • Langue d'enseignement : Both English and French
  • Méthode d'enseignement : En présence
  • Code : NEEC7D

Objectifs

At the end of the part dedicated to the design of the integrated linear regulator at the transistor level, the students can make the right choices regarding the topology improvement of the built-in analog functions due to the fact that they are able to analyze the main behavior of an analog circuit to determine its overall performances.

 

After the second part dedicated to the layout of the circuit using CadenceTM tools, the students will be able to draw the masks of an analog integrated circuit and make the relevant choices by showing that they master the concepts of component matching, required to implement specific properties such as the ratio of the transistor sizes or that of passive components.

Description

The project is divided into three main parts:

-1- The design at the transistor-level of the circuit using very simple 1st-order models of MOSFET transistors.

-2- Perform the circuit validation using Pspice/Spectre simulator involving the accurate technology parameters. First, several temperature cases have to be considered and finally all the worst-case parameters have to be taken into account to validate the sizing of the transistors. The influence of the dispersions is also highlighted by Monte Carlo analysis.

-3- Draw the layout of the circuit using CadenceTM tools with respect to the basic rules of component matching.

Compétences visées

- Know how to design and implement a linear regulator using a submicron CMOS technology,

- Have a deep understanding of the analog design flow,

- Be able to make the right choices concerning the transistor-level topology improvement,

- Obtain a good understanding the method of design of the analog circuit and the related Layout recommendations.

Bibliographie

R. Gregorian, G.C. Temes, “Analog MOS Integrates Circuits for Signal Processing” Wiley-Interscience

P.R. Gray, R.G. Meyer, “Analysis and Design of Analog Integrated Circuits”, Wiley

W. Sansen, “Advanced Anaolg IC Design Courses”, KU Leuven

K. Bult, “Transistor Level Analog IC Design Courses”, EPFL

Conditions d'admission

Knowledge of the basic concepts related to the transistor main characteristics (parameters, technology, MOSFET / BJT) as well as the basics of the analog design (common emitter/collector stage, input differential stage, push-pull, etc…).

Contact(s)

COUSINEAU Marc

Tél : 2431

Email : Marc.Cousineau @ enseeiht.fr

Lieu(x)

  • Toulouse

Contactez l’ENSEEIHT

L’École Nationale Supérieure d'Électrotechnique, d'Électronique, d'Informatique, d'Hydraulique et des Télécommunications

2, rue Charles Camichel - BP 7122
31071 Toulouse Cedex 7, France

+33 (0)5 34 32 20 00

Certifications

  • Logo MENESR
  • Logo UTFTMP
  • Logo INP
  • Logo INPT
  • Logo Mines télécoms
  • Logo CTI
  • Logo CDEFI
  • Logo midisup