VHDL - M1 ESECA
Objectifs
- Handle VHDL material description language
- Handle the architecture of an FPGA
- Be Autonomous on a project
Compétences visées
- VHDL programming
Pré-requis nécessaires
Prerequisites:
- Basis of analog and digital electronic (transistor, Flip-flop, LUT etc...)
Lieu(x)
- Toulouse